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PUBLICATIONS

   

   Updated 07/03/2024

    Total Number of Journal Papers(2008-2024) : 48

    Total Number of Conference Papers(2008-2024) : 71

    Total Number of Best Paper Awards(2008-2024) : 7

     

    Journal Publications (2008 – 2024, After Joining IIT)

2024

  1. Y. Kim, N. Alnatsheh, N. Yadav, J. Cho, H. Jo, and K. K. Choi, “A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes,” Electronics, vol. 13, no. 11, p. 2192, Jan. 2024.

2023

  1. N. Alnatsheh, Y. Kim, J. Cho, and K. K. Choi, “A Novel 8T XNOR-SRAM: Computing-in-Memory Design for Binary/Ternary Deep Neural Networks,” Electronics, vol. 12, no. 4, p. 877, Jan. 2023.
  2. V. H. Kim and K. K. Choi, "A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA," in IEEE Access, vol. 11, pp. 59438-59445, 2023.

2022

  1. J. Cho, S. Gong, and K. Choi, “A Study on High-Speed Outlier Detection Method of Network Abnormal Behavior Data Using Heterogeneous Multiple Classifiers,” Applied Sciences, vol. 12, no. 3, p. 1011, Jan. 2022.

2021

  1. N. Yadav, Y. Kim, S. Li, and K. K. Choi, “Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements,” Electronics, vol. 10, no. 21, p. 2724, Jan. 2021.
  2. Y. Kim, S. Li, N. Yadav, and K. K. Choi, “A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks,” Electronics, vol. 10, no. 17, p. 2181, Sep. 2021.
  3. Y. Kim, S. Patel, H. Kim, N. Yadav, and K. K. Choi, “Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles,” Electronics, vol. 10, no. 3, p. 256, Jan. 2021.

2020

  1. S. Li, Y. Luo, K. Sun, N. Yadav and K. K. Choi, "A Novel FPGA Accelerator Design for Real-Time and Ultra-Low Power Deep Convolutional Neural Networks Compared With Titan X GPU," in IEEE Access, vol. 8, pp. 105455-105471, 2020.
  2. S. Li, K. Sun, Y. Luo, N. Yadav, and K. Choi, “Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA,” Electronics, vol. 9, no. 5, p. 832, May 2020.
  3. N. Yadav, Y. Kim, M. Alashi, and K. K. Choi, “Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application,” Electronics, vol. 9, no. 3, p. 490, Mar. 2020.
  4. N. Yadav, Y. Kim, M. Alashi, and K. Ken Choi, “Design of a Voltage to Time Converter with High Conversion Gain for Reliable and Secure Autonomous Vehicles,” Electronics, vol. 9, no. 3, p. 384, Mar. 2020.
  5. Y. Kim, H. Kim, N. Yadav, S. Li, and K. K. Choi, “Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles,” Electronics, vol. 9, no. 3, p. 478, Mar. 2020.
  6. N. Yadav, M. Alashi, and K. K. Choi, “Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application,” Electronics, vol. 9, no. 3, p. 469, Mar. 2020.
  7. N. Yadav, Y. Kim, M. Alashi, and K. K. Choi, “A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design,” Electronics, vol. 9, no. 2, p. 326, Feb. 2020.

2018

  1. Y. Zhang, Y. Hong, and K. Choi, “Optimal energy-dissipation control for SOC based balancing in series connected Lithium-ion battery packs,” Multimedia Tools and Applications, Sep. 2018.

2017

  1. Qiang Tong, Ken Choi. “Activity Correlation Based Clustering Clock Gating Technique for Digital Filters,” International Journal of Electronics, Vol. 104, No. 7, pp 1095-1106, 2017
  2. Keunho Park, Ken Choi and TaeShik Shon, “A Study on Trace-Back Method of Financial Network Using IP Marking Server,”The Journal of Society for e-Business Studies, ISSN: 2288-3908, Vol., 22, No.4, Nov. 2017
  3. Seokcheol Lee, Sungjin Kim, Ken Choi and Taeshik Shon, “Game Theory-based Security Vulnerability Quantification for Social Internet of Things,”Future Generation Computer Systems, ISSN: 0167-739X, Vol., 82, Sept. 2017

2016

  1. Qiang Tong, Ken Choi, “A Review on System Level Low Power Techniques,”Journal of Pervasive Technology, Vol. 1, No. 1, pp 1-13, 2016
  2. Eui-Jik Kim, Jung-Hyok Kwon, Ken Choi and Taeshik Shon, “Unified Medium Access Control Architecture for Resource-Constrained Machine-to-Machine Devices,”ACM Transactions on Embedded Computing Systems (TECS), ISSN: 1539-9087, Vol., 15, Issue.2, May. 2016

2015

  1. Shuai Li, Joohee Kim, Ken Choi, “Distributed Video Coding with Background Modeling for Wireless Video Surveillance,”Journal of Pervasive Technology, Vol. 3. No 1., December 2015, pp 1- pp16

2014

  1. Junchao Wang and Ken Choi, “Analysis and Comparison among Four Structures of Adders Designed by Reversible logic,” in Proc. of UKC, Aug. 6-9, 2014
  2. Yunlong Zhang, Joohee Kim, Ken Choi and Taeshik Shon, “High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions,”International Journal of Distributed Sensor Networks, Vol. 2014, Mar 2014.

2013

  1. Li Li, Haiqing Nan and Ken Choi, “Activity Driven Fine-grained Clock Gating and Run Time Power Gating Integration,”IEEE Transactions on Very Large Scale Integration Systems (VLSI), TVLSI-00101-2011.R1, 2013
  2. Haiqing Nan and Ken Choi, “TDDB Monitoring and Compensation Circuit Design for Deeply Scaled CMOS Technology,” IEEE Transactions on Device and Materials Reliability, Issue 99, DOI: 10.1109/TDMR.2011.2167624, March 2013
  3. Li Li and Ken Choi, “Energy Efficient Encoder Design of Distributed Video Coding for Wireless Video Sensor Network,” International Journal of Information, July, 2013
  4. Haiqing Nan and Ken Choi, “Hardened latch design for deeply scaled CMOS technology,” International Journal of Information, July, 2013

2012

  1. Yuchi Tsao and Ken Choi, “Area-Efficient Parallel FIR Digital Filter Structures For Symmetric Convolutions Based on Fast FIR Algorithm,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), ISSN: 366-371, Vol., 20, No.2, Feb. 2012
  2. Yuchi Tsao and Ken Choi, “Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm,” IEEE Transactions on Circuits and Systems II-Express Briefs, pp. 371-375, Vol. 59, No. 6, Jun. 2012
  3. Haiqing Nan and Ken Choi, “High Performance, Low Cost and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology”, IEEE Trans. Circuits and Systems I, DOI 10.1109/TCSI.2011.2177135, Issue: 99, p.1-13, Jan 2012
  4. Jaeik Cho, Setiawan Soekamtoputra, Ken Choi, Taeshik SHon, JungTaek Seo, Jongsub Moon, “Power Dissipation and Area Comparison of 512-bit and 1024-bit Key AES”, Journal of Computers & Mathematics with Applications, Elsevier, Feb. 2012, DOI:10.1016
  5. Jaeik Cho, Taeshik Shon, Ken Choi, Jungtaek Seo, Jongsub Moon, “Simple Security Protocols based on EPC Global Generation,” Journal of Information of International Interdisciplinary, 2012
  6. Haiqing Nan and Ken Choi, “Low Cost and Highly Reliable Hardened Latch Design for Nanoscale CMOS Technology”, Elsevier Journal of Microelectronics Reliability, Vol. 52, Issue 6, P. 1209-1214, June 2012
  7. Jaeik Cho, Hojoon Lee, Ken Choi, Sangyep Nam, Jongsub Moon, “Visualization of Abnormal Behavior Detection using Parallel Coordinate and Correspondence Analysis, “ International Journal of Information, Vol. 15, No. 2, P. 2741-1749, 2012

2011

  1. Haiqing Nan, Kyungki Kim, Wei Wang, and Ken Choi, “Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits,” Journal of Information Processing System, March 31, 2011, pp. 93-102
  2. Haiqing Nan, Ken Choi, “Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology,” Elsevier Journal of Microelectronics Reliability, Vol. 51, P. 2086-2092, August 2011, ISSN 0026-2714, DOI: 10.1016/j.microrel.2011.07.048.
  3. Jaeik Cho, Taeshik Shon, Ken Choi and Jongsub Moon, "Dynamic learning model update of hybrid-classifiers for intrusion detection," The Journal of Super computing (SCI), Springer, DOI 10.1007/s11227-001-0698, Sept. 2011
  4. Heung-Shik Lee, Chongdu Cho, Alan T. Zehnder, and Kyu-won Choi," Development of micromagnetostrictive wireless controllable actuator," Journal of Applied Physics, 109, 07E501 (2011); doi:10.1063/1.3536525
  5. Li Li and Ken Choi, “Activity driven optimized bus specific clock gating for ultra-low-power smart space applications,” IET Communications (Formerly IEE Communications), Vol 5, Issue 17, P. 2501-2508, Nov. 2011
  6. Kyung Ki Kim and Ken Choi, “Hybrid CMOS and CNFET Power Gating in Ultra-Low Voltage Design,” IEEE Transactions on Nanotechnology, Vol10, No 6, Nov. 2011, pp1439-1448
  7. Yuchi Tsao and Ken Choi, “Cost-Reduced high speed architecture for Lattice Digital Filters based on cut-set localization,” IJIPT (International Journal of Internet Protocol Technology), Vol. 23, Issues 7, P. 2130-2137, Dec .2011
  8. Jaeik Cho, Manhyun Chung, Ken Choi, Yangsun Lee, Jongsub Moon, “Enhanced Security Protocols for EPC Global Gen2 on Smart Grid Network, ” International Journal of Sensors, Vol 7, Issue 11, P. 251-258, Dec, 2011

2010

  1. K. K. Kim, F. Ge, and K. Choi, “On-chip process variation monitoring circuit based on gate leakage sensing,” Electronics letters, vol. 46, no. 3, pp. 227–227, Jan. 2010.
  2. K. K. Kim, T. H. Han, and K. Choi, “Power grid aware timing analysis using S-parameter,” International journal of electronics, vol. 97, no. 7, pp. 759–772, Jul. 2010.
  3. K. K. Poornesh, S. Lee, C. Cho, and K. Choi, “Effect of bipolar plate materials on the stress distribution and interfacial contact resistance in PEM fuel cell,” International journal of precision engineering and manufacturing/International Journal of the Korean Society of Precision Engineering, vol. 11, no. 4, pp. 583–588, Aug. 2010.
  4. K. K. Kim, W. Wang and K. Choi, "On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 10, pp. 798-802, Oct. 2010.
  5. S. Lu, C. Cho, Kyu-won (Ken) Choi, W. Choi, S. Lee, and N. Wang, “An inscribed surface model for the elastic properties of armchair carbon nanotube,” Journal of mechanical science and technology, vol. 24, no. 11, pp. 2233–2239, Nov. 2010.

2009

  1. K. K. Kim, H. Nan and K. Choi, "Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 12, pp. 926-930, Dec. 2009.


    Conference Publications (2008 – 2024, After Joining IIT)

2019

  1. H. Kim and K. Choi, “Low Power FPGA-SoC Design Techniques for CNN-based Object Detection Accelerator, ” 2019 IEEE 10th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), pp. 1130-1134, 2019.
  2. H. Kim and K. Choi, “The Implementation of a Power Efficient BCNN-Based Object Detection Acceleration on a Xilinx FPGA-SoC, ” 2019 International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData), pp. 240-243, 2019.
  3. Sayali Patil, YoungBae Kim, Haiqing Nan, Li Li, Ken Choi, “Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB, ” 2019 IEEE International Conference on International SoC Design Conference(ISOCC). Best paper award
  4. Olivier Betschi, Ken Choi, “Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors, ” 2019 IEEE International Conference on International SoC Design Conference(ISOCC).

2018

  1. S.Patel, YoungBae Kim, Ken Choi, “Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory, ” 2018 IEEE International Conference on International SoC Design Conference(ISOCC), pp.44-45, 2018.
  2. YoungBae Kim, Ken Choi, “System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles", ” 2018 IEEE International Conference on International SoC Design Conference(ISOCC), pp.151-155, 2018.
  3. Shuai Li, Yukui Luo, Kuangyuan Sun, Ken Choi, “Heterogeneous System Implementation of Deep Learning Neural Network for Object Detection in OpenCL Framework, ” IEEE International Conference on Electronics, Information and Communication, Jan., 2018.

2017

  1. Kuangyuan Sun, Shuai Li, Yukui Luo, Raul Renteria, Ken Choi, “Highly-Efficient Parallel Convolution Acceleration by Using Multiple GPUs, ” IEEE International SoC Design Conference (ISOCC), Nov, 2017.
  2. Yukui Luo, Shuai Li, Kuangyuan Sun, Raul Renteria, Ken Choi, “Implementation of Deep Learning Neural Network for Real-time Object Recognition in OpenCL Framework, ” IEEE International SoC Design Conference (ISOCC), Nov, 2017.

2016

  1. Rahaprian M. Premavathi, Qiang Tong, Ken Choi, Yun Sik Lee. “A Low Power, High Speed, FINFET based 6T SRAM Cell with Enhanced Write and Read Stability, ” International SoCDesign Conference (ISOCC), pp. 311-312, Jeju,2016
  2. YoungBae Kim, Qiang Tong, Ken Choi, Yun SikLee. “Novel 8-T CNFET SRAM Cell Design for the Future Ultra-Low Power Microelectronics, ” International SoC Design Conference (ISOCC), pp. 243-244, Jeju, 2016
  3. Qiang Tong, Ken Choi. “A Review on System Level Low Power Techniques, ” Journal of Pervasive Technology, Vol. 1, No. 1, pp 1-13, 2016
  4. Shuai Li, Ken Choi, Yunsik Lee, “Artificial Neural Network Implementation in FPGA: A Case Study, ” IEEE International SoC Design Conference (ISOCC), Oct, 2016.
  5. Ken Choi, Shuai Li, Yukui Luo, “Convolutional Neural Networks (CNN) basic theories and recent developments, ” Chapter 4 in US-Korea Conference (UKC)/Korean-American Scientists and Engineering Association (KESA) Techbook "Smart Sensors and Deep Learning Solutions for Future Intelligent Systems - New Requirements from Software to Silicon", Springer, 2017.
  6. Heekyung Kim and Ken Choi, “A Modular Wireless Sensor Network for Architecture of Autonomous UAV using Dual Platform for Assisting Rescue Operation, ” 2016 IEEE SENSORS, pp. 1-3, Orlando, FL, 2016.

2014

  1. Junchao Wang and Ken Choi, “Analysis and Comparison among Four Structures of Adders Designed by Reversible logic, ” in Proc. of UKC, Aug. 6-9, 2014
  2. Shuai Li and Ken Choi, “Low power implementation technique for partitioned FSMs, ” in Proc. of UKC, Aug. 6-9, 2014
  3. Qiang Tong and Ken Choi, “A Review on System Level Low Power Techniques, ” ISOCC (International System-on-Chip Conference), Nov. 2014.
  4. Qiang Tong and Ken Choi, “A High Speed Pipeline Structure of Hardware Implementation for Block Classification for Distributed Video Coding, ” ISOCC (International System-on-Chip Conference), Nov. 2014.
  5. Haiqing Nan and Ken Choi, “Low Power Challenge and Solution for Advanced Mobile Device Design, ” ISOCC (International System-on-Chip Conference), Nov. 2014.

2013

  1. Jinkeon Kang, Seokhie Hong, Kai Lin, Yunlong Zhang, Joohee Kim and Ken Choi, “Multi-Purpose Bimodal Cryptographic Algorithm and Its Hardware Implementation, ” in Proc. of FTRA International Conference on Advanced IT Engineering and Management (FTRA-AIM13), Feb. 21-23, 2013
  2. Weidong Sun and Ken Choi, “Novel Glitch Reduction Techniques for Ultra-Low Power Digital Design, ” ISOCC (International System-on-Chip Conference), Nov. 2013.

2012

  1. Haiqing Nan and Ken Choi, “TDDB-Based Performance Variation of Combinational Logic in Deeply Scaled CMOS Technology, ” in International Symposium on Quality Electronic Design (ISQED) 2012
  2. Haiqing Nan and Ken Choi, “Soft Error Tolerant Latch Design with Low Cost for Nanoelectronic Systems,” IEEE International Symposium on Circuits and Systems (ISCAS), 2012
  3. Yu-Chi Tsao and Ken Choi, “Hardware-Efficient VLSI Implementation for 3-Parallel Linear Phase FIR Digital Filter of Odd Length,” IEEE International Symposium on Circuits and Systems (ISCAS), 2012

2011

  1. Li Li, Haiqing Nan, Ken Choi, “Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously” in International Symposium on Quality Electronic Design (ISQED) 2011
  2. Sandeep Suhas, Haiqing Nan, and Ken Choi, “Low Power Latch Design in Near Sub-threshold Region to Improve Reliability for Soft Error”, in International Symposium on Quality Electronic Design, 2011
  3. Feng Ge, Wei Wang, and Ken Choi, “A Circuit Prototype for Dielectric Polymer Energy Harvesting System”, in IEEE Green Technologies Conference, 2011
  4. Jaeik Cho, Manhyun Chung, Ken Choi, Yangsun Lee, and Jongsub Moon, “Enhanced Security Protocols for EPC Global Gen2 on Smart Grid Network”, in Enhanced Security Protocols for EPC Global Gen2 on Smart Grid Network, 2011
  5. Yu-Chi Tsao and Ken Choi, “Hardware-Efficient Parallel FIR Digital Filter Structures For Symmetric Convolutions”, in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2301-2301, June 2011
  6. Arun Ramnath Ramani and Ken Choi, “A Novel 9T SRAM Design in Sub-Threshold Region”, in IEEE Electro/Information Technology Conference (EIT) 2011
  7. Wei Wang, Zhiyuan Yu and Ken Choi, “High SNM 6T CNFET SRAM Cell Design Considering Nanotube Diameter and Transistor Ratio”, in IEEE Electro/Information Technology Conference (EIT) 2011
  8. Ho Joon Lee, Haiqing Nan, Kyung Ki Kim, and Ken Choi, “High Sensitivity and Low Power Skin Sensor Implementation and Performance Comparison using CMOS and CNFET”, in IEEE Electro/Information Technology Conference (EIT) 2011
  9. Yu-chi Tsao and Ken Choi, “Cost Reduction on High-Speed 1D IDCT Architecture based on Time Rescaling”, in IEEE Electro/Information Technology Conference (EIT) 2011
  10. Bohan Lin, Fan Wu, Haiqing Nan, and Ken Choi, “Near-Threshold Low Power Process Monitor for Deeply Scaled CMOS Technology”, in IEEE Electro/Information Technology Conference (EIT) 2011
  11. Zhiyuan Yu, Yinhui Chen, Haiqing Nan, Wei Wang and Ken Choi, “Design of a Novel Low Power 6-T CNFET SRAM Cell Working in Sub-Threshold Region”, in IEEE Electro/Information Technology Conference (EIT) 2011
  12. Peiwen He, Feng Ge, Wei Wang, Gyungsoo Kang, SooHyun Kim, and Ken Choi, “Simulation for Energy Harvesting System Based on Dielectric Electro Active Polymers”, in IEEE Electro/Information Technology Conference (EIT) 2011
  13. Yinhui Chen, Zhiyuan Yu, Haiqing Nan, and Ken Choi, “Ultralow Power SRAM Design in Near Threshold Region using 45nm CMOS Technology”, in IEEE Electro/Information Technology Conference (EIT) 2011
  14. Jaeik Cho, Kyuwon Choi, Taeshik hon, Jongsub Moon, "Enhanced NetwoWei Wang, Peiwen He, Setiawan Soekamtoputra, Feng Ge and Ken Choi, “Dielectric Electroactive Polymer (DEAP) Energy Harvesting System Forward Path Design for Different Vibration Input Patterns”, in IEEE Electro/Information Technology Conference (EIT) 2011
  15. rk Data Set Modeling Method and Its Evaluation Using MIT/LL Data Set", STA 2011 The 8th FTRA International Conference on Secure and Trust Computing, data anagement, and Applications (STA 2011)28-30 June, 2011 Crete, Greece
  16. Wei Wang, Yuchi Yuan, Peiwen He and Ken Choi, “Design Method for 6T CNFET Misalignment Immune SRAM Circuit”, IEEE MWSCAS, 2011
  17. Lili and Ken Choi, “Power efficient data retention logic design in the integration of power gating and clock gating”, IEEE MWSCAS (International Midwest Symposium on Circuits and Systems), 2011
  18. Sandeep Suhas, Haiqing Nan and Ken Choi, “A Novel Dual Edge Triggered Near-Threshold State Retentive Latch Design”, MWSCAS (International Midwest Symposium on Circuits and Systems), 2011
  19. Hojoon Lee, Haiqing Nan, Kyung Ki Kim and Ken Choi, “Sensor Interface Circuit for Artificial Skin Sensor Using CNFET”, MWSCAS (International Midwest Symposium on Circuits and Systems), 2011
  20. Yuchi Tsao and Ken Choi, “Cost-Reduced high speed architecture for Lattice Digital Filters based on cut-set localization,” in Proc. of FTRA International Symposium on Wireless Sensor Network Technologies and Applications for Smart Space (WTA), 2011
  21. Li and Ken Choi, Li “Energy Efficient Encoder Design of Distributed Video Coding for Wireless Video Sensor Network,” in Proc. of FTRA International Symposium on Wireless Sensor Network Technologies and Applications for Smart Space (WTA), 2011
  22. Haiqing Nan and Ken Choi, “Hardened latch design for deeply scaled CMOS technology,” in Proc. of FTRA International Symposium on Wireless Sensor Network Technologies and Applications for Smart Space (WTA), 2011
  23. Peiwen He, Wei Wang, Ken Choi, JongHyun Lee and SooHyun Kim, “Prototyping Circuit Design for Dielectric Electroactive Polymers Energy Harvesting,” ISOCC (International SoC Design Conference), Nov. 17-18, 2011

2010

  1. Feng Ge and Ken Choi “High Sensitivity UHF RFID Reader Baseband Design for EPC Class-1 Genration-2,” RFID Conference, April 14-16, 2010
  2. Feng Ge and Ken Choi “Novel Design and Implementation for Highly Sensitive Baseband Protocol of Class-1 Generation-2 UHF RFID System,” IEEE EIT Conference, May 2010
  3. Li Li and Ken Choi “SeSCG: Selective Sequential Clock Gating for Ultra-low-Power Multimedia Mobile Processor Design,” IEEE EIT Conference, May 2010
  4. Wei Wang and Ken Choi “Novel Cruve Fitting Design Methodology to Optimize Carbon Nanotube SRAM Cell,” IEEE EIT Conference, May 2010
  5. Haiqing Nan and Ken Choi “Novel CNFET SRAM Cell Design Operating in Sub-threshold Region Using Back-Gate Biasing,” IEEE EIT Conference, May 2010
  6. Kyung Ki Kim, Haiqing Nan, Ken Choi, "Power Gating for Ultra-Low Voltage Nanometer ICs", IEEE ISCAS, May 30-June 2, 2010
  7. Kyung Ki Kim, Haiqing Nan, Ken Choi, "Adaptive HCI-aware Power Gating Structure", IEEE ISQED, March 22-24, 2010
  8. KyungKi Kim, Haiqing Nan, and Ken Choi, “Hybrid MOSFET/CNFET Based Power Gating Structure,” IEEE SOCC, Spet 27-29, 2010
  9. Haiqing Nan, Ken Choi, “Novel Ternary Logic Design Based on CNFET”, in International SoC Design Conference (ISOCC), pp. 115-118, 2010
  10. Haiqing Nan, Kyung Ki Kim. Wei Wang, Ken Choi, “Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits” in International Symposium on Wireless sensor network Technologies and Applications (WTA) 2010
  11. Haiqing Nan, Ken Choi, “Novel Soft Error Hardening Design of Nanoscale CMOS Latch” in International SoC Design Conference (ISOCC), pp. 111-114, 2010
  12. Sandeep Sriram, Haiqing Nan, Ken Choi, “Dual Loop Hardened Latch Circuit for Low Power Application”, in International SoC Design Conference (ISOCC), pp. 123-126, 2010
  13. Li Li, Ken Choi, “Activity driven optimized bus specific clock gating for ultra-low-power smart space applications” in International Symposium on Wireless sensor network Technologies and Applications (WTA) 2010
  14. C. Cho, H. Lee, K. Choi and A Zehnder, “Development of micro magnetostrictive wireless controllable actuator”, in 55th Conference on Magnetism and Magnetic Materials, November 14-18, 2010, Atlanta, GA
  15. Jaeik Cho, Hojoon Lee, Ken Choi, Sangyep Nam, and Jongsub Moon, “Visualization of Abnormal Behavior Detection using Parallel Coordinate and Correspondence Analysis”, in International Symposium on Advanced in Cryptography, Security and Applications for Future Computing, 2010
  16. Jaeik Cho, Manhyun Chung, Ken Choi, Yangsun Lee, and Jongsub Moon, “Enhanced Security Protocols for EPC Global Gen2 on Smart Grid Network”, in 5th International Conf. on Ubiquitous Information Tech. and Applications, p. 1-5, Dec 2010
  17. Yu-Chi Tsao and Ken Choi, “A Simplified Flow for Synthesizing Digital FIR Filter Based on Common Subexpression Elimination” in International SoC Design Conference, pp. 174-177 2010

2009

  1. NamSung Kim and K-w Choi, and et. al., “Frequency and Yield Optimization using Power Gates in Power-Constrained Designs,” IEEE-ACM ISLPED (International Symposium on Low Power Electronics and Design 2009), San Francisco, CA, August 19-21, 2009
  2. W. Wang., Yu-Chi Tsao, K. Choi, S. Park, and M. Chung., “Pipeline Power Reduction through Single Comparator-based Clock Gating”inProceedings ofIEEEInternational SoC Design Conference (ISOCC 2009), pp.480 – 483, Dec. 2009
  3. Li Li and K-w Choi, “Selective Power Gating using Wasting Toggle Rate for Ultra-Low Power Processor Design,” IEEE EIT, p64-69, Ontario, Canada, 2009
  4. Feng Ge, Pranjal Jain and K-w Choi, “Ultra-Low Power and High Speed Design and Implementation of AES and SHA1 Hardware Cores in 65 Nanometer CMOS Technology,” IEEE EIT, p127-132, Ontario, Canada, 2009
  5. Haiqing Nan and Ken Choi, “Inter-Hierarchical Power Analysis Methodology to Reduce Multiple Orders of Magnitude Run-Time without Compromising Accuracy”, IEEE International SoC Design Conference, pp. 556-559, November, 24, 2009 (Best Paper Award)
  6. Li Li, Ken Choi, Seongmo Park and Moo-Kyoung Chung, "Novel RT level methodology for low power by using wasting toggle rate based clock gating", in International SoC Design Conference (ISOCC), pp. 484-487, 2009

Best Paper Award

  1. Lisantech Co., Ltd Award in 2019 IEEE International SoC Design Conference : S. Patil, Youngbae Kim, H. Nan, L. Li and Ken Choi,“Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB,” 2019 International SoC Design Conference (ISOCC), 2019, pp. 237-238
  2. IEEE CASS Seoul Chapter Award in 2018 IEEE International SoC Design Conference : S. Patel, Youngbae Kim and Ken Choi,“Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory,” 2018 International SoC Design Conference (ISOCC), 2018, pp. 44-45
  3. Best Paper Award in 2010 International Symp. on Wireless Sensor Netwrok and Technologies and Applications: Li Li, Ken Choi, et. al., “Energy Efficient Encoder Design of Distributed Video Coding for Wireless Video Sensor Netwrok”, International WTA Conference, Dec., 12-15, 2011
  4. Best Paper Award in 2010 International Symp. on Wireless Sensor Netwrok and Technologies and Applications: Jaeik Cho, Ken Choi, et.al, “Simple Security Protocols Based on EPC Global Generation 2”, International WTA Conference, Dec., 12-15, 2011
  5. LG Award in 2010 IEEE ISOCC: Haiqing Nan and Ken Choi, “Novel Soft Error Hardening Design of Nanoscale CMOS Latch”, IEEE International SoC Design Conference, November, 22, 2010
  6. Best Paper Award in 2010 International Symp. on Wireless Sensor Netwrok and Technologies and Applications: Li Li and Ken Choi, “Activity Driven Optimized Bus Specific Clock Gating for Ultra-Low-Power Smart Applications”, International WTA Conference, Dec., 9-10, 2010
  7. COSAR Award in 2009 IEEE ISOCC: Haiqing Nan and Ken Choi, “Inter-Hierarchical Power Analysis Methodology to Reduce Multiple Orders of Magnitude Run-Time without Compromising Accuracy”, IEEE International SoC Design Conference, November, 24, 2009

 

 

 

 

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