MOSIS Scalable CMOS (SCMOS) Design Rules

(Revision 7.2)

The MOSIS Service

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1.1 SCMOS Design Rules

This document defines the official MOSIS scalable CMOS (SCMOS) layout rules. It supersedes all previous revisions.

In the SCMOS rules, circuit geometries are specified in the Mead and Conway's lambda based methodology [1]. The unit of measurement, lambda, can easily be scaled to different fabrication processes as semiconductor technology advances.

Each design has a technology-code associated with the layout file. At the moment, three technology-codes are used to specify the basic CMOS process. Each technology-code may have one or more associated options added for the purpose of specifying either (a) special features for the target process or (b) the presence of novel devices in the design. At the time of this revision, MOSIS is offering six CMOS processes from three different foundries with feature sizes from 2.0 micron to 0.5 micron.

2 Standard SCMOS

The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET devices [3].

2.1 Well Type

Three technology-codes are used to indicate the well type (substrate) used for fabrication (as shown in Table 1).

Designs specifying the SCE technology-code may be fabricated in any CMOS process, N-well or P-well (either) and must include both wells (and correspondingly, well/substrate contacts for proper bias). For any given fabrication process the 'other' well be ignored during mask generation. If twin-tub processes are offered in the future, both wells will be used. Note: Currently MOSIS only offers n-well processes.

2.2 SCMOS Options

SCMOS options are used to designate projects that use additional layers beyond the standard single-poly, double metal CMOS. Each option is called out with a designator that is appended to the basic technology-code. Please note that not all possible combinations are available. The current list is shown in Table 2.

In addition to the options in Table 2, two undeclared options exist. The first is for high voltage MOSFET. The second is for a tight metal rule for metal interconnect. For options available to specific processes, see Tables 3a and 3b.

MOSIS currently offers the fabrication processes shown above in Tables 3a and 3b. For each process the list of appropriate SCMOS technology-codes is shown. Note that whenever SCNxx appears, SCExx is also appropriate.

2.4 SCMOS_SUBM - Sub Micron Rules

The SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. To take full advantage of advanced submicron processes, the SCMOS rules were revised to create SCMOS_SUBM. By increasing the lambda size for some rules (those that didn't shrink as fast in practice as did the overall scheme of things), the submicron rules allow for use of a smaller value of lambda, and better fit to these small feature size processes. Table 4 lists the differences between SCMOS, SCMOS tight metal and SCMOS sub-micron.

A user design submitted to MOSIS using the SCMOS rules can be in either Calma GDSII format [2] or Caltech Intermediate Form (CIF version 2.0) [1]. The two are completely interchangable. Note that all submitted cif and gds files have already been scaled before submission, and are always in absolute metric units -- never in lambda units.

GDSII is a binary format, while CIF is a plain ASCII text. For detailed syntax and semantic specifications of GDS and CIF, refer to [2] and [1] respectively.

In GDS format, a design layer is specified as a number between 0 and 255 (formerly 63). MOSIS SCMOS now reserves layer numbers 21 through 62, inclusive, for drawn layout. Layers 0 through 20 plus layers 63 and above can be used by designers for their own purposes and will be ignored by MOSIS.

In this revision, nine new layers were added as shown below:

P-high-voltage is used to indicate high-voltage p-type areas.

N-high-voltage is used to indicate high-voltage n-type areas.

MEMS-open is used to indicate substrate pit opening area for MEMS devices.

MEMS-etch-stop is used to indicate substrate p+ etch-stop area for MEMS devices.

Contact replaces the previously separate poly-contact, active-contact and electrode-contact layers.

Pads is used to indicate bonding pad locations.

Explicit field implant denotes the field implant reversal layer.

Poly-cap supports the AMI-style linear capacitor called SCNPC. It has the regular (two-metal) SCN layers, plus the new layer POLY_CAP1.

Silicide block is used for blocking the siliciding of poly and/or active.

Users should be aware that there is only one contact mask layer, although several separate layers were defined and are retained for backward compatibility. A complete list of SCMOS layers is shown in Table 5.

References

[1] C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980

[2] Cadence Design Systems, Inc./Calma. GDSII Stream Format Manual, Feb. 1987, Release 6.0, Documentation No. B97E060

[3] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley, 2nd edition, 1993

On HP's CMOS14 process (and probably on all subsequent processes as they evolve), HP requires that ALL features on the insulator layers (CONTACT, VIA, VIA2) MUST BE of the single standard size; there are no exceptions for pads (or logos, or anything else); large openings must be replaced by an array of standard sized openings.

The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 5.2, then that rule, 5.2, may be replaced by these rules, which reduce the overlap, but increase the spacing to surrounding features. The remaining rules above, 5.1, 5.3, and 5.4, still apply as originally stated.

The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 6.2, then that rule, 6.2, may be replaced by these rules, which reduce the overlap, but increase the spacing to surrounding features. The remaining rules above, 6.1, 6.3, and 6.4, still apply as originally stated.

The new layer in this option is the electrode layer, which is a second polysilicon layer (physically above the standard, or first, poly layer). The oxide between the two polys is the capacitor dielectric. The capacitor area is the area of coincident poly and electrode.

The new layer in this option is the pbase layer, which is an active area that is implanted with the pbase implant to form the base. The base contact is enclosed in p-select. The emitter is an n-select region within (and on top of) the base. The entire pbase sits in an n-well that is the collector. The collector contact is a well contact, but the overlaps are larger.

This illustration applies only to CMOS34. Note that the smaller values apply only to CMOS34; the larger values apply to CMOS14.

This illustration applies only to CMOS34. Note that the smaller values apply only to CMOS34; the larger values apply to CMOS14.

A fourth metal layer will be available around the time of the 0.5 um feature size regime. In processes with four metal layers, the third metal is made thinner and therefore has the same layout rules as the second metal. Rules 15.1 and 15.3 are therefore revised in this option. These rules are designed for the SUBM variant directly.

Rule	Description	Lambda
15.1	Minimum Metal3 width	3 (not illustrated)
15.3	Minimum Metal3 overlap of VIA2	1 (not illustrated)
21.1	Exact size	2 x 2
21.2	Minimum spacing	4
21.3	Minimum overlap by Metal3	1

Table 28: SCMOS Layout Rules - Via3 (Quad Metal Option)

Rule	Description	Lambda
22.1	Minimum width	6
22.2	Minimum spacing to Metal4	6
22.3	Minimum overlap of Via3	2

Table 29: SCMOS Layout Rules - Metal4 (Quad Metal option)

Rule	Description	Lambda
23.1	Minimum POLY_CAP1 width This is lithographic; the minimum to build a real capacitor is greater than 12 lambda	8
23.2	Minimum spacing, POLY_CAP1 to POLY_CAP1 (neighboring capacitor)	4
23.3	Minimum spacing, POLY_CAP1 to ACTIVE (all capacitors must be over field)	8
23.4	Minimum overlap, POLY_CAP1 over POLY	3
23.5	Minimum overlap, POLY_CAP1 over CONTACT	2
23.6	Minimum overlap, POLY over CONTACT (in a capacitor only; still 1 lambda elsewhere)	2
23.7	Minimum spacing, POLY to CONTACT-to-POLY_CAP1	2
23.8	Minimum spacing, unrelated METAL1 to POLY_CAP1	4
23.9	Minimum spacing, METAL2 to POLY_CAP1	2

Table 30: SCMOS Layout Rules - SCNPC with POLY_CAP1